Design and Implementation of Embedded Large Screen LED Display

LED, large screen, embedded, display screen

1 Introduction

The application of LED display screen has been more common, and with the popularization of application, more new LED display screens will be used in more occasions. Therefore, it is of great practical significance to study the display of embedded large screen dot matrix LED.

But now a variety of LED displays in the market have different display performance, and most of them need the host computer to control the display process in real time. This paper presents an optimized high-performance and high reliability embedded large screen LED display system. Only one FPGA and two SRAM can realize the drive and content replacement of large screen LED display. It can be said that its performance has been greatly improved. This design can deal with a variety of occasions with large screen display.

2 system hardware design and Implementation

There are many and flexible ways of hardware connection, which directly affects the performance of display. The hardware connection mode given below is the optimal mode, which can achieve high-performance display and make software writing simple.

Each 8 × The LED dot matrix block of 8 is called the minimum module. 8 per 16 × The LED dot matrix block of 8 is a base module. There are 8 base modules in the transverse direction and 2 minimum modules in the longitudinal direction, as shown in Figure 1. Each small square in the figure represents a minimum module.

The control signals of each minimum module are 8 line signals H1 H8 and 8 data signals R1 R8. The line signal is connected to the output of a 38 decoder 74HC138, and its input is hangq [2.. 0]; The column signal is connected to the data signal of this row with the output of a 74HC595, as shown in Figure 2.

74HC595 is a shift latch chip. It has a shift register, a data move in pin (DS), a data move out pin (Q8), 8 data output pins (Q1 Q8), pulse signal (CLK) and data latch signal (st). Its working principle is that when the pulse signal acts, the data moved into the pin will be moved into the shift register inside the chip. When the 8-bit data is fully moved, the data of the 8th bit will appear on the data removal pin. If a pulse signal is given, the data of this bit will be removed and new data will be moved in. When the data latch signal is valid, the shift register inside the chip latches 8-bit data to 8 data output pins to realize data output.

For a minimum module, when the data signal R is valid, the clock signal tsck will move the data into the internal register of 74HC595. After all 8 bits of the internal register are filled with data, the latch signal tlock is valid, and all the filled data can be sent to the 8 data signals R1 R8. At this time, use hangq [2.. 0] to select a line signal. After the line latch signal tleden is valid, it can be displayed in this 8 × Data display is realized on the point array of 8. Because at a specific time can only be in this 8 × One line is displayed on the LED dot matrix block of 8, so the first line to the eighth line are displayed in turn. As long as the speed is fast enough, the human eye looks continuous.

For a base module, because each smallest module has a 74HC595 shift latch chip, as long as the 74HC595 of each smallest module is connected in series, that is, the data out pin of the previous 74HC595 is connected to the data in pin of the next 74HC595, and the pulse signal and data latch signal of 74HC595 are connected to the same signal, the data display of a base module can be realized. Like the smallest module, only one row of all the smallest modules in the base module can be displayed at a specific time. As long as the speed is fast enough during the display of 8 lines in turn, the human eye can't see the flicker.

In this way, the above 16 base modules are connected together. Data and control signals enter from the right and output from the left. A base module is 64 × 16 LED dot matrix block, the display scale in this design is 512 × 512 dot matrix, so it is necessary to connect 8 horizontal and 32 vertical minimum modules. In the actual design, it is divided into the upper half screen and the lower half screen, 512 respectively × 256。 When the data is filled with the upper half of the screen and then the lower half of the screen, the data latch signal and line latch signal are finally given, so as to realize the display of a line of the smallest module of the whole screen. Of course, to realize the display of the whole screen data, only 8 lines of the smallest module in the whole screen are displayed circularly.

In the upper half of the screen display, it is divided into 8 512 × 32. Such a block is called a separate display module, that is, the horizontal 2-line base module is regarded as a separate module and controlled with a separate group of signals, and the upper half of the screen needs 8 groups of signal control. These 8 groups of signals are the same except for the data signal R. In other words, in the upper half of the screen display, eight data lines simultaneously string data to the eight separate display modules on the upper half of the screen. Of course, it is only to fill a row of the smallest module in the separate display module with data, and then input data to the lower half of the screen. Therefore, the situation of the lower half screen is basically the same as that of the upper half screen. In addition to the 8 groups of data signals R, there are also different clock signals. When inputting data, the clock signal of the upper half screen is effective first. According to the theory of the basic module, 2048 pulses must be input before the data of the upper half screen is filled; Then the data on the lower half screen is valid, so the data on the lower half screen can be input. The situation is exactly the same as that on the upper half screen.

In terms of display control, one FPGA chip of Altera company is used, the model is epf10k20tc1444, and two SRAM chips are used, each with a capacity of 128KB, which are used to store the display data (see Figure 3).

During operation, FPGA only takes out the displayed data from one of the two SRAMs for display at a specific time, while the other SRAM exchanges data with MPU, and MPU will write new data so that FPGA can display the data of this SRAM in the next time period, so as to work alternately. If the displayed image does not change, that is, when the data in one SRAM remains unchanged, MPU does not need to write data to another SRAM. At this time, the embedded display module can work independently of MPU. The data size of a frame is 32KB, which is far less than the capacity of SRAM, so some display skills can be added when writing the program, such as displaying from top to bottom.

From the above, FPGA has two basic functions: one is to take out data from an SRAM and display it on the display screen; The other is to write the data given by MPU to another SRAM.

3 software design

The software design shall be prepared according to the connection of hardware, which is mainly divided into display part and write ram part (see Figure 4).

In the scanning display, firstly, the clock pulse signal of 8 groups of control signals on the upper half of the screen is valid, and in this process, the data signal R of 8 groups of control signals is valid, so a row of the smallest module among the 8 separate display modules on the upper half of the screen can be filled with data first. Then fill a row of the smallest module of the eight separate display modules on the lower half of the screen with data in the same way. Of course, the upper half of the screen and the lower half of the screen are filled with the same row of the smallest module. Finally, the data latch signal and row latch signal are valid to display. In this process, we should pay attention to the data signal R, because to display the data of the whole screen, in the process of software writing, if we want to accurately display the data displayed at a certain position at that position, we should accurately take out the data from the memory.

The data size displayed in each frame is 32768b, which fully meets the requirements for the alternative operation of two ram blocks. Moreover, SRAM has fast access speed and can display the expected data well when changing frames. A ram selection module is used in the program to select which ram to read or write at a certain time.

The signals connected between FPGA and memory are am1a [16.. 0], ram1d [7.. 0], ram1rd, ram1wr; Ram2A[16..0], Ram2D[7..0], Ram2Rd, Ram2Wr。 When FPGA takes out data from ram1 for display, the signal related to ram1 is valid; At the same time, write data to ram2. The program also uses four internal variables RT [7.. 0] [7.. 0], GT [7.. 0] [7.. 0], RS [7.. 0] [7.. 0] and GS [7.. 0] [7.. 0] to represent four arrays respectively, and each array has 8 bytes.

A global clock CLK is used in the program to drive an internal global signal counter_ Temp, it's a 15 bit vector. The tsck and tnsck signals take 8 CLK clock cycles as their 1 clock cycle, that is, 8 CLK times send 1-bit data. The timing of FPGA reading ram is as follows: first, the address signal appears on ramxa [16.. 0], then ramxrd and ramxwr are set to low level and high level respectively. After 12 15ns, the read data will appear on ramxd [7.. 0], so that FPGA can read this number for display.

The timing of FPGA writing ram is controlled by external MPU signal. First, the address signal appears on ram2a [16.. 0], then ramrd and ramwr are set to high level and low level respectively, and the written data appears on ram2d [7.. 0]. After a short time, the data is written.

The program sets ram1d and ram2d in FPGA as two-way ports, which can be written and read. Corresponding buffer shall be set inside. Because writing ram is written from MPU to ram, MPU should indicate the address and data to be written, so there should be an address and data input port in the program. In the actual design, in order to reduce the port of fp2ga, it is designed as a low address and data multiplexing line ad [7.. 0], which is selected by one signal ale; When it is low level, the valid data of ad [7.. 0] is the address, and when it is high level, it is the data to be written to ram.

In the process of still image display, in order to make the eyes look not flickering, it is necessary to display a frame of image at least 50 times in a second, even if a frame of image is displayed at most 20ms. To meet this requirement, it is necessary to make the 8 lines of a minimum module complete a cyclic display within 20ms at most. Because the upper half screen and the lower half screen transmit data separately, it is required to transmit half screen data within 1.25ms at most, and the clock cycle needs to be 0.6 μ S, and the clock frequency of the selected FPGA can reach more than 50MHz, which fully meets the display requirements.

4 Conclusion

Hardware connection and software design are integrated. In the initial overall planning of the system, we should give consideration to both. From the hardware connection to the final software implementation, this design is the result of optimization. Therefore, the software designed according to the hardware connection in this design can realize such a large-scale dot matrix display only with a 20000 gate FPGA. Moreover, the LED display screen of this design is very clear and stable, and can be smooth and free in the process of changing frames without stagnation.