Design of LED Color Lamp Controller Based on 51 Single Chip Microcomputer

With the continuous improvement and beautification of people's living environment, colored neon lights can be seen on many occasions. LED color lamps have been widely used because of their rich lighting colors, low cost and simple control. Decorating with color lamps has become a fashion. However, at present, most of the LED color lamp controllers in the market are realized by full hardware circuit, with complex circuit structure and single function. In this way, once the finished products are made, they can only flash according to the fixed mode, and the dynamic parameters such as lighting time, mode and flashing frequency can not be adjusted according to the needs of different occasions and different time periods. The structure of this color lamp controller often has the disadvantages of too many chips, complex circuit, large power loss and so on. In addition, from the perspective of functional effect, there are few lighting modes and monotonous styles, which lack user operability and affect the lighting effect. Therefore, it is necessary to improve the existing color lamp controller.

2 design principle

2.1 MCS51

Pin description

MCS MCU adopts 40 pin dual in-line package. Figure 1 shows the pin arrangement diagram. The description of 40 pins is as follows:

(1) Main power pins VSS and VCC

â‘  VSS grounding

â‘¡ VCC is a 5V power supply during normal operation

(2) External crystal oscillator pins xtal1 and xtal2

â‘  The input of the inverting amplifier of xtal1 internal oscillation circuit is a pin of the external crystal. When an external oscillator is used, this pin is grounded.

â‘¡ Xtal2 internal oscillation circuit is the output of inverting amplifier. Is the other end of the external crystal. When an external oscillator is used, this pin is connected to an external oscillator source.

Fig. 1 8051 pin arrangement

(3) Control or multiplex pins RST / VPD, ale / prog, EA and / VPP with other power supplies

â‘  Rst / VPD when the oscillator is running, the high level of two machine cycles (jump from low to high) appears on this pin, which will reset the MCU

During VCC power down, this pin can be connected to the standby power supply, and the VPD provides the internal standby power supply to maintain the data in the internal RAM.

â‘¡ During normal operation of ale / prog, ale function (allowing address latch) is provided to latch the low byte of address to the external latch, and ale pin periodically sends positive pulse signal at a constant frequency (1 / 6 of oscillator frequency). Therefore, it can be used as an external output clock or for timing purposes. However, it should be noted that when accessing the external data memory, an ale pulse will be skipped, and the ale terminal can drive (absorb or output current) eight LSTTL circuits. For EPROM single chip microcomputer, during EPROM programming, this pin receives the programming pulse P impulse (PROG function)

â‘¢ PSEN external program memory read strobe signal output terminal is valid twice in each machine cycle during fetching instructions (or data) from external program memory. Eight LSTTL inputs can also be driven.

â‘£ EA / VPP and EA / VPP are internal program memory and external program memory selection terminals. When EA / VPP is at high level, access the internal program memory; when / VPP is at low level, access the external program memory.

For EPROM single chip microcomputer, during EPROM programming, 21 V EPROM programming power supply (VPP) is added to this pin.

(4) Input / output pins p0.0 - p0.7, P1.0 - P1.7, p2.0 - p2.7, P3.0 - P3.7.

â‘  Port P0 (p0.0 - p0.7) is an 8-bit open drain bidirectional I / O port. When accessing external memory, it is a time-sharing low byte address and data bus. Port P0 can drive eight LSTTL loads by absorbing current.

â‘¡ Port P1 (P1.0 - P1.7) is an 8-bit quasi bidirectional I / O port with internal lift resistance. Can drive (absorb or output current) four LSTTL loads

â‘¢ P2 port (p2.0 - p2.7) is an 8-bit quasi bidirectional I / O port with internal lifting resistance. When accessing external memory, it outputs the high 8-bit address. P2 port can drive (absorb or output current) four LSTTL loads.

â‘£ Port P3 (P3.0 - P3.7) is an 8-bit quasi bidirectional I / O port with internal lifting resistance. It can drive (absorb or output current) four LSTTL loads.

2.2 LED display nixie tube

LED has two types: common cathode and common anode. As shown in the figure. The cathodes of the diodes are connected together. Usually, the common cathode is grounded, while the common anode connects the anodes of the light-emitting diodes together and is connected to a voltage of 5V. One digit display is composed of 8 light-emitting diodes, of which 7 light-emitting diodes form each stroke (segment) a g of font "8", and the other decimal point is DP light-emitting diode. When a certain forward voltage is applied to a certain section of LED, the stroke of that section is on; Dark without voltage. In order to protect each section of LED from damage, additional current limiting is required.

Schematic diagram of LED nixie tube structure

The 20 pin functions of AT89C2051 chip are:

VCC supply voltage.

GND grounding.

Rst reset input. When RST goes high and remains for 2 machine cycles, all I / O pins are reset to "1".

The input of xtal1 reverse oscillation amplifier and the input of internal clock working circuit.

Xtal2 is the output from the reverse oscillation amplifier.

P1 port 8-bit bidirectional I / O port. Pins P1.2 P1.7 provide internal pull-up. When they are used as input and pulled down to low level externally, they will output current due to internal pull-up. P1.0 and P1.1 need external pull-up, which can be used as the forward input (ain0) and reverse input (ain1) of the on-chip accurate analog comparator. The P1 port output buffer can receive 20mA current and directly drive the LED display; P1 port pin can be used as input after writing "1". During flash programming and programming verification, P1 port can also receive encoded data.

P3 port pins P3.0 p3.5 and P3.7 are seven bidirectional I / 0 pins with internal pull-up. P3.6 is internally connected to the on-chip comparator output and cannot be accessed as a general I / O pin. The output buffer of P3 port can receive 20mA perfusion current; After P3 port writes "1", it is pulled up internally and can be input. Port P3 can also be used as a special function port.

2.3 interrupt command

When the CPU and peripherals exchange information, there is a contradiction between fast CPU and slow peripherals. Sometimes emergencies may occur inside the machine. Therefore, interrupt technology is usually used in the computer.

The CPU and the peripheral work in parallel. When the peripheral data is ready (or some emergency occurs), the CPU makes a request to the CPU. The CPU suspends the executing program and turns to serve the peripheral (or handle the emergency). After processing, it returns to the original breakpoint and continues to execute the original program.

Interrupt priority: when multiple interrupt sources apply to the CPU for interrupt at the same time, the CPU gives priority to the interrupt request that needs the most urgent processing, and then responds to the lower priority after processing. This is the pre arranged response order.

Nesting of interrupts: in the interrupt system, high priority interrupt requests can interrupt the ongoing lower level interrupt source processing,

(1) Interrupt technology is a common technology in real-time control. 51 Series MCU has three internal interrupts and two external interrupts. The so-called external interrupt is the signal required to generate an interrupt on the external pin.

Each interrupt source has a fixed entry address of the interrupt service program (called vector address or vector address). When the CPU responds to the interrupt, the internal hardware of the MCU ensures that it can automatically jump to the address. Therefore, this address should be memorized. In the assembler, the interrupt service program should be stored in the correct vector address.

(or deposit a transfer order); In C language, it is automatically set by the keyword n of interrupt n.

(2) The interrupt of the single chip microcomputer is managed by the internal register, which is the interrupt permission register IE and the interrupt priority register IP. The CPU must turn on the interrupt, that is, turn on the global interrupt switch EA and turn on the interrupt switch of each interrupt source, so that the CPU can respond to the interrupt request of the interrupt source, one of which is indispensable.

(3) From the surface of the program, the main program and interrupt service program seem to be unrelated. Only by mastering the process of interrupt response can we understand the occurrence and return of interrupt, understand the interrupt program, and write high-quality interrupt program.

Table 2.1 common interrupts

Symbol name interrupt cause interrupt service program entry

INT0 external interrupt low level or falling edge signal 0003h of 0p3.2 pin

INT1 external interrupt 1

P3.3 pin low level or falling edge signal 0013h

T0 timer 0 interrupt timer counter 0 count back to zero overflow 000BH

T1 timer 1 interrupt timer counter 1 count back to zero overflow 001bh

T2 timer 2 interrupt timer counter 2 interrupt (TF2 or t2ex signal) 002bh

The Ti / ri serial port interrupts the serial communication and completes the transmission or reception of one frame of data, causing the interrupt 0023h

3 hardware schematic diagram

The crystal oscillator (12Mhz) is timed for 1 second. For 12Mhz crystal oscillator, its clock cycle T = 1 / F = 1 / 12us, while a machine cycle of 89C51 includes 12 clock cycles, so a machine cycle is 1US. For T0, make it work at 16 bit, and the maximum timing is 65536 * 1 = 65536us. It needs multiple timings to achieve one second timing.

4 software design

4.1 flow chart

4.2 source program

ORG 0000H ; Interrupt entry program;

LJMP START

ORG 0003H

RETI

ORG 000BH

RETI

ORG 0013H

RETI

ORG 001BH

RETI

CLEAR： RET; ; Initialization program

; START:ACALL CLEAR ; Main program

STAR1:MOV P3，#0FFH

JNB P3.2，FUN2

JNB P3.3，FUN3 ; Close button

JNB P3.4，FUN0

JNB P3.5，FUN1

JNB F0，STAR1 ; Once a key was pressed F0 to set 1

RET;

FUN0:LCALL DL10MS ; Eliminate jitter

JB P3.4，STAR1

WAITL0:JNB P3.4，WAITL0 ; Wait for key release

SETB F0

FUN01:LCALL FUN00

LCALL STAR1

LJMP FUN01;

FUN1:LCALL DL10MS ; Eliminate jitter

JB P3.5，STAR1

WAITL1:JNB P3.5，WAITL1 ; Wait for key release

SETB F0

FUN10:LCALL FUN11

LCALL STAR1

LJMP FUN10;

FUN2:LCALL DL10MS ; Eliminate jitter

JB P3.2，STAR1

WAITL2:JNB P3.2，WAITL2 ; Wait for key release

SETB F0

FUN20:LCALL FUN22

LCALL STAR1

LJMP FUN20;

FUN3:LCALL DL10MS ; Eliminate jitter

JB P3.3，STAR1

WAITL3:JNB P3.3，WAITL3 ; Wait for key release

CLR F0

MOV P1，#0FFH ; Off display

LJMP STAR1;

FUN00:MOV A，#0FEH ； Moving from P1.0 to P1.7 illuminates

FUN000:MOV P0，A

LCALL DL05S

JNB ACC.7，OUT

RL A

AJMP FUN000

OUT： RET;

FUN11:MOV A，#0FEH ； Turn on from P1.0 to P1.7

FUN111:MOV P1，A

LCALL DL05S

JZ OUT

RL A

ANL A，P1

AJMP FUN111;

FUN22:MOV A，#0FEH ； Interval lighting

FUN222:MOV P1，A

LCALL DL01S

CPL A

RL A

MOV P1，A

LCALL DL01S

RET;

FUN33： MOV A，#01H ； Point by point extinction

FUN333： MOV P1，A

LCALL DL01S

JNZ OUT

RL A

ORL A，P1

AJMP FUN333

DL01S:MOV R2，#0FFH ; Delay procedure

MOV R7，#02H

LOOP1： DJNZ R2，LOOP1

LOOP5：DJNZ R7，DL512

RET

DL10MS:MOV R3，#14H

LOOP2： LCALL DL512

DJNZ R3，LOOP2

RET

DL05S:MOV R4，#0AH

LOOP3： LCALL DL10MS

DJNZ R4，LOOP3

RET

DL30S:MOV R5，#03H

LOOP4:LCALL DL05S

DJNZ R5，LOOP4

RET

END

4.2 one second timing program

MOV B，#0AH ； Allow interrupt

MOV TMOD，#01H ； Working mode 1

MOV TH0，#0B0H

MOV TL0，#3CH

SETB TR0 ï¼› Start count

SETB EA ï¼› Open interrupt

BU:JBC TF0，SHI

SJMP BU

SHI:MOV TH0，#3CH

MOV TL0，#0B0H

RET